Data processing system



April 16, 1968 ADELAAR ET AL 3,378,818

DATA PROCES S ING SYSTEM 3 Sheets-Sheet .1

Filed April 22, 1964 April 16, 1968 H. H. ADELAAR E AL 3,378,818

DATA PROCESSING SYSTEM I5 Sheets-Sheet Filed April 22, 1964 UnitedStates Patent Office Patented Apr. 16, 1963 3,378,818 DATA PROCESSINGSYSTEM Hans llelmut Adelaar, Ekeren, Jean Louis Masure, Wilrijk, and FeTsi Chu, Antwerp, Belgium, assignors to International Standard ElectricCorporation, New York, N.Y., a corporation of Delaware Filed Apr. 22,1964, Ser. No. 361,692 Claims priority, application Netherlands, May 7,1963, 292,449 23 Claims. (Cl. 340-1725) ABSTRACT OF THE DISCLOSURE Adata processing system for controlling an automatic switching system. Aplurality of logic circuits, controlled by a wired configuration, areable to perform the more routine switching control operations. The dataprocessor is central to the logic, commonly controlled, and able toperform the more complex non-routine operations. As long as the logiccircuits are able to handle the switching requirements of the system,they do so. But, when the operations become too complex, the logiccircuits request the processing system to intervene. When it does so,virtually all logic circuits stop their operations while the requestinglogic circuit and the processor exchange information.

The prcsent invention relates to a data processing system such as usedfor controlling an automatic telecommunication switching system,including a plurality of logical circuits which are each able to performone or more routine operations, and a common control circuit forcoordinating said routine operations.

Such a system is already known; however, this known system is controlledby timed pulses which define a repetiiivc time cycle having In timepositions, one per logical circuit, and said common control circuitoffers its servive to each logical circuit during the portion of thecycle allocated to this logical circuit.

This means that even when a logical circuit does not need theintervention of the common control circuit, a time position is providedtherefor. Generally the time required by such a logical circuit forperforming a routine operation is much longer than a time cycle. so thatduring most of these cycles this logical circuit will not require theintervention of the common control circuit. Hence. a considerable timewill be lost. This is also due to the fact that the duration of the timeposition allocated to a logical circuit must be chosen sutliciently longto enable the longest intervention by the common control circuit to beperformed. On the other hand, when a logical circuit needs theintervention of the common con trol circuit and when this interventionis needed at a moment which is not situated within the allocated timeposition, this logical circuit will have to wait for an intervention ofthe common control circuit until the latter presents its service again.Due to this delay it is obvious that information which is onlytemporarily present in the logical circuit may be lost.

It is therefore an object of the present invention to provide a systemof the above type wherein these drawbacks are removed.

The present system is characterized by the fact, that said commoncontrol circuit is able to perform non routine or more complexoperations and that each of said logical circuits is able to eventuallyrequest for an intervention of said common control circuit upon aroutine operation having been performed or depending on the result of aroutine operation after this operation has been performed.

The above mentioned and other objects and features of the invention willbecome more apparent and the invention itself will be best understood byreferring to the following description of embodiments taken in c0njunction with the accompanying drawings in which:

FIG. 1 is a schematic diagram of a system according to the invention;

FIG. 2 shows in detail the part indicated by A in FIG. 1;

FIG. 3 represents the stop request logical circuit, part of this system;

FIG. 4 is a timing diagram.

Referring to FIG. 1, the present telecommunication system includes thelogical circuits MU, to MU associated with a common memory addressdistributor MAD, the logical circuits AC to AC and a common controlcircuit CCC. These logical circuits are able to perform one or moreroutine operations and the common control circuit CCC is able tocoordinate these routine operations and to perform non routine or morecomplex opperations.

The logical circuits AC to AC which are periodically operated each havethree output leads, namely an information output lead I" to 1" a stoprequest output lead SR" to SR and a stop condition output lead SC" toSC",,. The information output leads 1" to 1",, are connected to the busbar BB in the common control circuit CCC via the coincidence gates G toG respectively, the stop request output leads SR" to SR" are directlyconnected to the stop request logical circuit SRLC in this commoncontrol circuit CCC and the stop condition output leads SC' to SC" areconnected to the bus bar BB via the coincidence gates G; to 6'respectively. The coincidence gates G, to G are controlled by a logicalcircuit LC via the bus bar It whereas the coincidence gates G to G arecontrolled via the bus bar 1 by a central programming unit CPU includedin the common control circuit CCC.

Referring to FIG. 2, the memory unit MU and the memory addressdistributor MAD represented in FIG. 1 are shown in detail. The memoryaddress distributor MAD comprises a drive current pulse generator PG,the output of which constitutes a first input of the threeinputcoincidence gates K and K The second inputs of these gates areconstituted by the O-output and the l-output of the bistate device Prespectively, whereas the third inputs of these gates are constituted bythe Ooutput of the bistate device E. The output of the gate K isconnected to the input of a cyclic address selector CA5 which is of awell known type and which is constituted by an array of gates (notshown) controlled by a binary counter C the output of the last stage ofwhich is connected to the l-input of the bistate device P. The O-outputof the bistate device P is connected to the last stage of a binary timecounter TC. The output of the gate K is connected to the input of acyclic address selector CAS which is also constituted by an array ofgates (not shown) controlled by a binary counter C The cyclic addressselector CAS and CAS: control the address registers AR and ARrespectively, the outputs of which are connected to the inputs of thememory units MU to MU, as indicated by the multiplying arrow.Hereinafter only the memory unit MU is described in detail. The outputof the address register AR, is connected to one input of the two-inputmixer M the other input of which is connected to the bus bar BB in thecommon control circuit CCC via the lead AI, and the coincidence gate R,(FIG. 1). The output of the address register AR is connected to oneinput of the two-input mixer M the other input of which is connected tothe above bus bar BB via the lead AI' and the coincidence gate R, (FIG.l). The outputs of the mixers M and M are connected to the inputs of thedecoder units DC and DC: respectively, the outputs of which areconnected to the random access selectors RAS and RAS; which are of awell known type, such as for instance disclosed in the book Square- LoopFerrite Circuitry, by C. J. Quartly and published by Iliife Books Ltd.,London, 1962, page 83. The random access selectors RAS and RAS eachcontrol a twocoordinate memory matrix MM and MM;, respectively. Anoutput of the memory matrix MM is connected to the junctor scanningcircuit JSC and to the junctor scanning logical circuit JSLC, whereas aninput thereof is connected to the bus bar BB via the lead I and thecoincidence gate S (FIG. 1). An output of the memory matrix MM isconnected to the line scanning logical circuit LSLC, whereas an inputthereof is connected to the bus bar BB via the lead 1' and thecoincidence gate S' (FIG. 1).

The outputs of the junctor scanning logical circuit JSIJC and of theline scanning logical circuit LSLC are connected to the input of thestop logical circuit SLC via the leads S and S respectively. The outputlead SR of the latter circuit SLC is directly connected to the stoprequest logical circuit SRLC in the common control circuit CCC, whereasthe output lead 5C is connected to the bus bar BB via the coincidencegate T (FIG. 1).

The coincidence gates R to R R' to R',,, S to S and S, to S in thememory units MU to MU are controlled by the central programming unit CPU(FIG. 1) via the bus bar 1 whereas the coincidence gates are controlledby the logical circuit LC via the bus bar k.

Hereinafter, and although they are able to perform other functions, itis described how the memory units MU to MU are able to perform calldetection and call supervision routine operations.

The memory matrix included in each of the memory units MU to MUcomprises a plurality of words, e.g. 256, each storing all theinformation relating to a particular call and more particularly theidentity of the junctor used for the establishment of this call and alsothe previous states of the relays included in this junctor andindicating the subscriber loop condition. The memory matrix MM: includedin each of the memory units MU to MU comprises a plurality of words,e.g. 1000, each storing the line and parking bits of a particular line.

The addresses of the words of the memory matrixes MM; and MM; are storedin the address registers AR and AR; respectively. It is supposed thatcorresponding words in the various memory matrixes MM; of the memoryunits MU to MU have a same address, and that this is also the case withcorresponding words in the memory matrixes MM: of these memory units.Due to this, corresponding words of the memory matrixes MM; or MM may beinterrogated in parallel as well during call supervision as during calldetection.

The call supervision routine operation is performed in a mannerhereinafter described. Supposing the bistable devices P and B being inthe condition shown, the drive current pulses supplied by the pulsegenerator PG are delivered via the gate K to the cyclic addressdistributor CAS; which cyclically scans the address register AR Eachaddress read is supplied via the mixer M to the decoder circuit DC;which then delivers the decoded address in parallel to all the randomaccess selectors RAS which read corresponding words in the correspondingmemory matrixes MM In this manner the identity of a particular junctorand the previous states of the relays thereof are staticized in eachmemory unit. There they are transferred to the associated junctorscanning circuit JSC and junctor scanning logical circuit JSLC,respectively. Upon receiving the identity of the particular junctor, thejunctor scanning circuit PSC scans the present states of the relays ofthis junctor via the lead s The latter states are then transferred tothe above junctor scanning logical circuit JSLC via the lead s wherethey are compared with the previous states of the junctor relays alreadytransferred thereto. From the information received the junctor scanninglogical circuit JSLC deduces if a modification in the states of thejunctor relays has occurred or not. Due to the fact that a word addresshas been supplied to all the memory matrixes MM in parallel suchinformation is simultaneously obtained for p junctors.

When a modification is detected in a memory unit, the output lead 8 ofthe associated junctor scanning logical circuit JSLC is activated and inresponse thereto the associated stop logical circuit SLC activates theassociated request output lead, SR to SR which is conccted to the commoncontrol circuit CCC. in this manner the intervention of the lattercircuit is requested for performing more complex operations. The stoplogical circuit SLC also registers the so called stop condition, i.e.the reason way the output lead S has been activated. This stop conditionmay be transferred later, when needed, to the common control circuit CCCvia the output lead SC to SC and the associated coincidence gate T to T1n case no modification has been detected the following word isinterrogated in each of the memory matrixcs MM; and a new callsupervision routine operation is performed. From the above it followsthat, by the stop condition, it is indicated that the described callsupervision routine operation has led to the detection of a modificationof the condition of a subscriber loop. By the stop request signal, it isindicated that for further treating this modification the common controlcircuit CCC has to intervene. Such a call supervision routine operationis performed within 20 microseconds. The request for an intervention ofthe common control circuit CCC by one of the memory units MU to MU iscalled a stop request since simultaneously with such an intervention thecyclic scanning operation of the memory matrixes MM in the other memoryunits is stopped. This is necessary in order to enable transfer ofinformation from or towards these memory matrixes MM via the leads I toI Al to Al the associated coincidence gates S to S R to R respectivelyand the bus bar BB, but also in order that no further interventionrequests would be originated by these other memory niatrixes. Indeed,such new requests would be lost, unless a special buffer store would beprovided for registering these requests. Such a butler store howevercomplicates the system.

The call detection routine operation is performed in a mannerhereinafter described. Supposing the bistable B being in the O-conditionshown and the bistable device P in the l-condition, the drive currentpulses supplicd by the pulse generator PG are delivered, via the gate Kto the cyclic address distributor CAS which cyclically scans the addressregister AR Each address read is supplied via the mixer M to the decodercircuit DC which then delivers the decoded address in parallel to allthe random access selectors RAS; which read corresponding words in thecorresponding memory matrixes MM In this manner the line and parkingbits of a particular subscriber line are thus staticized in each memoryunit. There they are transferred to the associated line scanning logicalcircuit LSLC. Simultaneously and in synchronism with the scanning of aword in a memory matrix MM a line scanner not shown) scans the loopcondition of the corresponding subscriber, this loop condition beingalso transferred to the line scanning logical circuit LSLC via the lead8 From the information received, the latter circuit then deduces if theline has made a new call or not. Due to the fact that the word addresshas been supplied to all the memory matrixes MM in parallel the latterinformation is simultaneously obtained for p lines.

It should be noted that a call detection operation such as describedabove is known from the article Outlines of a TDM Two-Wire TelephoneSwitching System and Its Control, by H. H. Adelaar, F. A. Clemens and.l. Masure published in llEE 1961, volume 108, part B.

In case no new call is detected, the next word in each of the memoryunits is interrogated, and the above described call detection routineoperation is again performed in each of these units.

When a new call is detected in a memory unit, the output lead of theassociated line scanning logical circuit LSLC is activated and inresponse thereto the stop logical circuit SLC activates the associatedstop request output lead, SR to 811, which is connected to the commoncontrol circuit CCC. In this manner the intervention of the lattercircuit is requested for performing more complex operations. The stoplogical circuit SLC also registers the so called stop condition orreason why the lead 5 has been activated, i.e. in the present case for anew call. This stop condition may be transferred later, when needed, tothe common control circuit CCC via the output lcad SC; to SC and theassociated coincidence gate T to T,,.

Summarizing, by the above stop condition it is indicated that the abovedescribed call detection operation, which consists in scanning a lineand the corresponding word in a memory matrix MM: and processing theinformation thus obtained in a line scanning logical circuit LSLC hasled to the detection of a new call. By the above stop request signal itis indicated that for further treating this call the common controlcircuit CCC has to intervene. Such a call detection routine Operation isperformed within 20 microseconds. lt should be noted that the requestfor an intervention of the common control circuit CCC by one of thememory units MU, to MU is again called a stop request, sincesimultaneously with such an intervention the cyclic scanning operationof the memory matrixcs MM in the other memory units has to be stoppedfor the same reasons as mentioned in relation with the call supervisionroutine operation. Information may be transferred from or towards thesememory matrixes via the leads I, to I,,, Al' to AI',,, the associatedgates S, to 5' R to R and the bus bar BB.

The above aperiodically operated logical circuits AC to AC are also ableto perform routine operations, but these routine operations are supposedto be much longer than those performed by the memory units MU to MU Amarker hunting circuit is able to search for a free path between asubscriber and a free junctor, a marker driving circuit is able tooperate switches for establishing this path, etc. Principally referringto FIG. 1, when one of these aperiodically operated circuits AC to AChas for instance become free or has finished a routine operation andrequires new information in order to be able to perform another routineoperation, an intervention of the common control circuit CCC has to berequested. This is indicated by the activation of the stop requestoutput lead SR" to SR" which is connected to the common control circuitCCC. A stop condition, indicating why a stop has been requested, isregistered and may be transferred later, when needed, to the commoncontrol circuit CCC via the output lead SC" to SC,,, the associated gate6' to G and the bus bar BB. It should be noted that in case a stoprequest is granted to one of the aperiodically operated circuits, thecyclic scanning of the memory units MU to MU is again to be stopped forthe same reasons as mentioned in relation with the call supervision andthe call detection routine operations. Transfer of information from ortowards these aperiodically operated logical circuits AC to AC may beperformed via the leads 1" to 1" the gates G to G respectively and thebus bar BB.

From the above it follows that an aperiodically operated circuit as wellas a cyclically operated circuit may request for the intervention of thecommon control circuit CCC and that the cyclic operation of the memoryunits is each time stopped when such an intervention is performed.

It has been described how during each call supervision routine operationa junctor scanning circuit JSC scans the states of a number of junctorrelays which indicate the loop condition of a particular subscrilcrline. In order to be able to detect modifications in the condition ofthis loop due to a subscriber dialling a number, it has been found thatreckoning with the dialling speed, this scanning operation has to beperformed at least once during a period of 10 to 12 milliseconds, e.g.10.24 milliseconds. Therefore, the call supervision routine opera tionson the 256 words in each of the memory matrixes MM, of the memory unitsMU, to MU have to be performed at least once during such period. Since,as mentioned above each routine operation takes 20 microseconds, the 256call supervision routine operations may be performed during 5.12milliseconds, so that there remains 5.12 milliseconds per period of10.24 milliseconds for performing other operations, as will be explainedhereinafter.

It has also been described above that interventions of the commoncontrol circuit CCC may be requested by the memory units MU to MU in thecase of a new call or of a subscriber loop modification or by theaperiodicnlly operated circuits AC to AC Intervention requests in caseof subscribers loop modifications must immediately be granted since theconditions indicating such loop modifications are only temporarilypresent and therefore require immediate intervention of the commoncontrol circuit. The conditions indicating new calls remain presentduring a relatively long time and the conditions indicating interventionrequests from aperiodically operated logical circuits are continuouslypresent and are not so urgent. Therefore the granting of requests inboth these cases may be delayed.

Summarizing, in each 10.24 miiliseconds period, 256 call supervisionroutine operations and eventual interventions of the common controlcircuit CCC upon subscriber loop modifications having been detected mustnecessarily be performed. The eventual remaining time of each period maybe used for performing call detection routine operations and forinterventions of the common control circuit upon new calls having beendetectcd or upon requests having been made by aperiodically operatedlogical circuits. Hence, there exists a problem of determining at anytime of the above period of 10.24 milliseconds if the last mentionedoperations may be performed or not. This can obviously be done in anumber of ways and one possible solution is hereinafter described indetail.

According to this solution the 256 call supervision routine operationsare performed at the beginning of each period of 10.24 milliseconds andmay eventually be interleaved with interventions by the common controlcircuit upon requests by the memory units in case of loop modificationsor from aperiodically operated circuits. Only when these 256 routineoperations have been finished, call detection routine operations areexecuted eventually interleaved with interventions by the common controlcircuit upon requests by the memory units in case of new calls or fromaperiodically operated circuits. The routine operations of theaperiodically operated circuits are performed during the callsupervision and call detection routine operations. The interventionrequests from the memory units MU to MU and from the aperiodicallyoperated logical circuits AC to AC are granted according to a prioritywhich decreases following the series MU to MU AC to AC,,.

Principally referring to FIG. 3, there is shown a stop request logicalcircuit SRLC for registering the requests from the various circuits andfor determining whether requests from these circuits can be granted ornot. This stop request logical circuit SRLC comprises a stop requestregistering circuit, a request granting means and a timing arrangement.The request granting means are itself constituted by a lockout circuit,other registering means and an inhibition circuit.

The output or stop request leads SR to SR and SR, and SR of the logicalcircuits MU to MU and AC to AC respectively are connected to thel-inputs of the associated bistate devices A to A and B to B,, whichconstitute the request registering circuit Hence, also in the series ofbistate devices A to A and B to E the priority decreases from left toright. The l-output of each of the bistate devices A to A constitutes aninput of a coincidence gate X to X,,, another input of which isconnected to the O-output of the bistate device E which is also shown inFIG. 2. The output lead of each coincidence gate X to X is connected tothe l-input of a bistate device C to C the l-output to of which iscoupled to the 0-input of the bistate devices A to A via a two-inputcoincidence gate Z to Z the other input of which is connected to aninput terminal T. Moreover, each gate X to X has inputs which areconnected to the O-outputs a, to a' of the preceding bistate devices inthe series A to A For instance, the gate X has inputs connected to theO-outputs a' to a' of the bistate devices A; to A The l-outputs [2 to bof the bistate devices B to B are connected to input leads of thecoincidence gates Y Y respectively. An input lead of these gates isfurther connected to the O-inputs of the above bistate device E.Moreover, each gate Y to Y has inputs which are con nected to theD-outputs (1' to a' b, to b',, of the preceding bistate devices in theseries A; to A,,, B to B For instance, the gate Y has inputs connectedto the O-outputs a' to a' and b; of the bistate devices A to A and 8;.Finally, input leads of the gates Y to Y are connected to the O-outputof the bistate device F, the l-input and the O-input of which areconnected to the outputs of the mixers W and W respectively, in cludedin a timing arrangement which will be described later. The output leadsof the coincidence gates Y to Y are connected to the l-inputs of thebistate devices D to 13 respectively. The l-outputs d to d of thebistate devices D to D are coupled to the O-inputs of the bistatedevices B, to 13,, respectively via the two-input coincidence gates U,to U the other inputs of Which are connected to the above input terminalT, which is also connected to the O-inputs of the bistate devices E, C;to C and D to D via the delay circuit D.

The 1-input of the above bistate device E is connected to the output ofa mixer W the inputs of which are connected to the output leads to c andd; to d,, of all the bistate devices C to C and D to D The above lockout circuit is constituted by the gates X to X, and Y to Y Indeed, theoutput of a coincidence gate in the series X to X Y to Y cannot beactivated when the l-output of the bistate device A to A B to Bassociated to a lower numbered coincidence gate is activated. The aboveother registering means are constituted by the bistate devices C to Cand D to D and the above inhibition circuit is constituted by the bistate device F. The timing arrangement includes the remaining part ofFIG. 3 and will further be described in detail.

The operation of the above described part of the stop request logicalcircuit SRLC will now be described in detail. Hereby it is supposed thatall the bistate devices included therein are initially in theirO-condition. When one of the logical circuits MU to MU or AC to AC,,,e.g. MU which is performing a call supervision or a call detectionroutine operation, requests for the intervention of the common controlcircuit CCC by activating its request output lead SR the correspondingbistate device A is triggered in its l-condition. Due to this, thecorresponding bistate device C is also triggered in its l-condition viathe gate X thus indicating that the stop request is granted to thememory unit MU The gates Y to Y,, are all inhibited by the O-output a ofthe bistate device A,,. These gates and the gates X, to X are alsoinhibited by the O-oulput of the bistate device E which has beentriggered in its l-condition by the l-output c of the bistate device Cvia the mixer W In this manner no other requests can be granted. Alsothe coincidence gates K and K (FIG. 2) are inhibited so that the callsupervision or call detection routine operation is stopped. It should benoted that in case a request for an intervention is granted to anaperiodically operated circuit, the bistate device E will also betriggered in its l-condition and the operation of the memory units willbe stopped. On the contrary, when a request is granted to a memory unitthe operation of the aperiodically operated circuits will not bestopped, so that the latter will continue their routine operation.

From the above it follows that requests from the logical circuits MU toMU and AC to AC are granted according to their priority since a requestfrom a particular logical circuit having been registered in one of thebistate devices A to A B to E all requests from a logical circuit with alower priority are prevented from being granted. This request will onlybe granted when no logical circuit with a higher priority has originateda request.

The bistate device E in its l-condition indicates that a request hasbeen granted and is being treated by the common control circuit CCC.After the latter circuit has finished its more complex operations, theinput terminal T is activated and due to this, the bistate device A istriggered back in its O-condition via the coincidence gate 2 A smalltime interval later, determined by the delay circuit D, the bistatedevices C and E are both also triggered back in their O-condition and anew routine operation is started.

in the above description, it has been supposed that the bistate device Fis in its O-condiion. in this manner a request from an aperiodic-allyoperated logical circuit will always be granted on condition that thereare no rcqucsts from other logical circuits with a higher priority andthat the common control circuit is not treating a request, the lastcondition being indicated by the bistate device E in its 0-condi.ion.Notwithstanding this and as mentioned above, it may happen that anintervention request from an aperiodically operated circuit must berefused for timing reasons, i.e. when otherwise the 256 supervision rouine operation could not have been performed within the required intervalof 10.24 milliseconds. The timing arrangement which decides for grantingthe request or not will now be described. It includes the binary counterC (FIG. 2) which is of a well known type and which is constituted byeight intercoupled binary stages M to M (not shown) so that it is ableto count 256. As already mentioned above, this binary counter C is usedfor counting the 256 addresses of the cyclic address distributor CAS andhence of the 256 words of the various memory matrixes MM Next to thisword counter the timing arrangement also includes the binary timecounter TC (FlG. 2). This counter is also of a well known type and isconstituted by nine inlercoupled binary stages M' to M';; (not shown).It is stepped each 20 microseconds by pulses delivered by a pulsegenerator (not shown). This time counter is hence able to count 5 2 20or 10.24 milliseconds. Principally referring to FIGS. 3 and 4. in orderthat the 256 call supervision rouline operations should be performedwithin the above time interval of T:l0.24 milliseconds. the following isdone. At the time position T :4.48 ms. it is checked in what posidon theword counter C, has arrived. If the position attained is smaller than128 it is decided not to grant intervention requests from aperiodicallyoperated logical circuits during 1.92 milliseconds. If the positionattained is however situated between 128 and 192 it is decided not togrant intervention requests from aperiodically operated logical circuitsduring 1.28 milliseconds. Finally. if the position attained is higherthan 192 all intervention requests are granted. At the time position T332 ms. it is again checked in what position the word counter C hasarrived and if this position is smaller than 228 it is decided not togrant intervention requests from aperiodically operated circuits during0.64 millisecond. On the contrary when the position attained is higherthan 228 such intervention re quests are granted.

At the above time position T :4.48 ms, the time counter TC is in theposition 224 i.e. the binary stages M' M' and Mq are in theirl-condition. The l-outputs of these stages are indicated by 1W RT andII} and constitute the inputs of the gate V the output of which is henceactivated at the time position T during 20 microseconds. At the timeposition T :8.32 ms., the time counter is in the position 416 i.e. thebinary stages M' M'; and M' are in the l-condition. The l-outputs ofthese binary stages are indicated by H' H and H' and constitute theinputs of the gate V the output of which is hence activated at the timeposition T during 20 micro seconds.

When the word counter is in a position between and 128 the binary stageM the O-output of which is in dicated by M is still in its O-condition.When the word counter is in a position between 128 and 192, the binarystages M and M-, are in their D-condiiion and l-condition respectively.The O-output of M which is indicated by M and the l-output of M which isindicated by M constitute the inputs of the coincidence gate V Finally,when the word counter is in a position between 192 and 224, the binarystage M is in its O-condition whereas the binary stages M and M are inthe l-condition. The 0- output of the binary stage M and the l-outputsof the binary stages M and M are indicated by M H and fi respectivelyand constitute the inputs of the coincidence gate V In order to check ifat time position T the word counter is in a position between 0 and 128,the above output M; and the output of the above gate V are connected tothe inputs of a coincidence gate V the output of which is connected, onthe one hand, to the l-input of the bistate device F via the mixer Wand, on the other hand, to the l-input of the bistate device R. Thesebistate devices F and R are hence triggered in their l-condition when attime position T the word counter is not yet in position 128. In order tocheck if at time position T the word counter is in a position between128 and 192, the outputs of the above gates V and V are connected to theinputs of a coincidence gate V the Output of which is connected to thel-input of the bistate device F via the mixer W This bistate device F ishence triggered in its l-condition when at the time position T the wordcounter is in a position between 128 and 192. Finally, in order to checkif at time position T the word counter is in a position between 192 and224, the outputs of the above gates V and V; are connected to the inputsof a coincidence gate V the output of which is connected to the l-inputof the bistate device F via the mixer W This bistate device F is hencetriggered in its l-condition when at the time position T the wordcounter is in a position between 192 and 224.

Summarizing, the bistate device F is brought in its l-condition firstwhen at the time position T the word counter is in a position between 0and 128, second when at the time position T the word counter is in aposition between 128 and 192 and finally when at the time position T theword counter is in a position between 192 and 224. In all these casesthe gates Y, to Y are inhibited by the non-activated O-output of thebistate device F, so that intervention requests from the aperiodicallyoperated logical circuits AC to AC will then not be granted.

In the above first case, the requests have only not to be granted duringa time interval t =l.92 ms. and therefore the bistate device F has to bereset in its (It-condition at the time position T =T +t =4.48+1.92=6.40rns. At this moment the time counter is in the position 320 wherein thebinary stages M' and M are in their l-condition. The l-outputs of thelatter binary stages which are indicated by 1T and M' are connected tothe inputs of the coincidence gate V the output of which is henceactivated at the time position T =6.40 ms. The output of the latter gateV is connected to the O-input of the bistate device F which is hencereset in its O-condition at the above time position T In the abovesecond case, the requests have only not to be granted during a timeinterval t =l.28 ms. and therefore the bistate device F has to be resetin its O-condition at the time position T4=T1+t2 4.48 mS.+I.28 HIS- 5 761118.

At this moment the time counter is in the position 288, wherein thebinary stages M and M';, are in their l-condition. The l-outputs of thelatter binary stages which are indicated by M and M' are connected tothe inputs of a coincidence gate V the output of which is henceactivated at the time position T :5.76 ms. The output of the latter gateis connected to the O-input of the bistate device F via the coincidencegate V which is controlled by the O-output of the bistate device R andthe mixer W In this manner, the bistate device F is only reset in itsO-condition at the time position T,,, when the bistate device R is inits O-condition, i.e. when it has been detected, at time position T thatthe word counter C is in a position which is larger than 128. In thecase that the latter position is smaller than 128, the bistate device Fwill be reset in its O-condition at the moment T Indeed, in this casethe bistable device R is in its l-condition and the gate V is inhibited.At the moment T the bistate device R is also reset in its O-condition.

In the above third case the requests have only not to be granted duringa time interval t =0.64 ms. and therefore the bistate device F has to bereset in its O-condition at the time position At this moment the timecounter is in the position 448, wherein the binary stages M'.;, M'-; andM are in their l-condition. The l-outputs of the latter binary stages,

which are indicated by M M' and M',, are connected to the inputs of thecoincidence gate V the output of which is hence activated at the timeposition T =8.96 ms. The output of the latter gate is connected to theO-input of the bistate device P which is hence reset at the above timeposition T At the moment the word counter C reaches its 256th or finalposition, the bistate device P (FIG. 2) is triggered in its l-conditionso that the gates K and K are inhibited and opened respectively and thatthe call detection routine operations are automatically started. At themoment the time counter TC has reached its final position, i.e. at theend of each 10.24 Ins. period, the bistate device P is reset in itsO-condition so that the gates K and K are opened and inhibitedrespectively and that the call detection operations are stopped and thecall supervision operations are started.

From the above it follows that in the present system the various logicalcircuits request themselves for an intervention of the common controlcircuit, contrary to the system according to the above mentioned BelgianPatent No. 589,466 where this common control circuit regularly presentsits service to these logical circuits. The advantages of this new mannerof operation are that considerable time is saved since no fixed timepositions are allocated to the various logical circuits and that theduration of each intervention is also not fixed but only dependent onthe nature of the intervention. Hence the flexibility of the presentsystem is high.

In the above described solution the requests from the memory units MU,to MU either in case of call supervision or call detection, haveabsolute priority over the requests from the apcriodically operatedcircuits AC to AC,,, the latter requests having a priority decreasingfrom AC to AC and being only granted when enough time remains in the10.24 milliseconds period.

This particular solution has only been given by way of example and manyother solutions are possible. The only object which has always to befulfilled is that the 256 call supervision routine operations beperformed within the 10.24 milliseconds period. For instance, instead ofcontrolling the gates X, to X Y, to Y in the manner shown in FIG. 3, onecould control each of these gates by means of the associated bistatedevice A to A 8; to B and by one or more inhibition bistate devices,such as F, themselves controlled by a timing arrangement. The lattercould for instance operate according to a priority table in order tovary the priority of the various logical circuits, by conditioning theinhibition bistate devices, in dependence on the time position of arequest within the above 10.24 ms. period and on the nature of thelogical circuit originating such request. For example this system, couldoperate in such a manner that at time position I of the period only therequests of the circuits AC and AC; are granted, but that at timeposition t only the requests of the circuits AC and AC are granted etc.

Principally referring to FIGS. 1 and 3, when a request has been grantedto one of the logical circuits AC to AC or MU; to MU the identity ofthis circuit which is registered in the corresponding bistate device Dto D or C, to C is transferred to the logical circuit LC via the outputleads c to e d, to d and registered therein. As soon as this hashappened, the logical circuit LC controls the corresponding gate G toG',,, T to T via the bus bar kin order to transfer the stop condition ofthe corresponding logical circuit AC to AC MU; to MU to this logicalcircuit LC via the bus bar m. In this logical circuit LC the aboveidentity and the last mentioned stop condition are processed so as toform input information for a central programming unit CPU which will notbe described in detail. This central programming unit CPU is forinstance able to control the transfer of information from the logicalcircuits AC, to AC,,, MU, to MU towards the unit and via the bus bar BBby controlling the gates G to G S to S S to 8' to process theinformation received from the logical circuit LC and from the logicalcircuits AC to AC and MU to MU and to control the transfer of theinformation thus obtained towards the latter logical circuits.

In the above described system when a request is originated both theoutput leads SR and SC are simultaneously activated, the first SR givingthe identity of the logical circuit originating this request and thesecond SC giving the reason for which this request is originated. Sinceonly the output leads SR are coupled to request registering means, thepriority of the various requests is only dependent on the identities ofthe requesting logical circuits and not on the reasons of the requests.

According to another possible solution, the logical circuits may beprovided with one or more output leads SR each of which, when activated,gives an indication as well concerning the identity of the requestinglogical circuit as concerning the reason why for which a request isoriginated. By connecting each of these output leads to a requestregistering means, the priority with which the requests are granted willobviously be dependent as well on the identity of the requesting logicalcircuit as on the reason of the requests. Since in this case the stopcondition is automatically combined with the stop request, nocombination is necessary in the logical circuit LC.

While the principles of the invention have been described above inconnection with specific apparatus, it is to be clearly understood thatthis description is made only by way of example and not as a limitationon the scope of the invention.

What is claimed is:

1. Data processing system, such as used for controlling an automatictelecommunication switching system, including a plurality of logicalcircuits which are each able to perform one or more relatively simpleroutine operations, a common control circuit means for coordinating saidroutine operations, means in said common control circuit for performingnon-routine relatively complex operations and means associated with saidlogic circuits and said common control circuit for requestingintervention of said common control circuit when a routine operation isperformed or depending on the result of a routine operation, after theroutine operation has been performed.

2. Data processing system, in particular automatic tele' communicationsystem, including a plurality of first logical means each for performingat least one first or routine operation and second logical means forperforming second or more complex operations, each of said first logicalmeans including a requesting means to request for an intervention ofsaid second logical means upon a first or routine operation having beenperformed or depending on the result of a routine operation after thisoperation has been performed.

3. Data processing system as claimed in claim 1, char acterized in thatsaid common control circuit includes a request logical circuitcomprising a plurality of request registering means each serving forregistering a request and request granting means for granting therequests in accordance with the priority with which said common controlcircuit has to intervene.

4. Data processing system as claimed in claim 2, wherein said secondlogical means includes a request logical circuit comprising a pluralityof request registering means each for registering a request and requestgranting means for granting the requests in accordance with the prioritywith which said second logical means has to intervene.

5. Data processing system as claimed in claim 3 wherein said requestgranting means includes a plurality of gating means each controlled byone of said request registering means, a plurality of other registeringmeans, and a priority arrangement means for controlling said gatingmeans responsive to the requests registered in said request registeringmeans for operating only the one gate with the highest priority which isregistered in one of said other registering means.

6. Data processing system as claimed in claim 5, characterized in thatsaid plurality of logical circuits or said plurality of first logicalmeans includes a number of first logical circuits which have each toperform a sequence of q identical routine operations within apredetermined time interval and that said priority arrangement is soarranged and so designed that intervention requests from said firstlogical circuits have absolute priority over the intervention requestsfrom the remaining or second of said plurality of logical circuits orfirst logical means.

7. Data processing system as claimed in claim 6, characterized in thateach of said first logical circuits includes a register with q words anan auxiliary logical circuit, each of said routine operations consistingin interrogating one of said Words and in processing the thus obtainedinformation in said auxiliary logical circuit.

8. Data processing system as claimed in claim 7, characterized in thatit includes stopping means for stopping said sequence of q routineoperations of said first logical circuits during an intervention of saidcommon control circuit.

9. Data processing system as claimed in claim 8, characterized in thatsaid priority arrangement is constituted by a plurality of inhibitionmeans each controlling one or more of said gating means and by a timingarrangement controlling said inhibition means in such a manner that oneor more, of said inhibition means are operated during distinct timeintervals thus inhibiting the controlled gating means and preventingcorresponding requests from being registered in said other registeringmeans.

10. Data processing system as claimed in claim 9, characterized in thatsaid timing arrangement includes a first counter for counting said qroutine operations, a second counter for counting said predeterminedtime interval, and checking means for checking at various positions ofsaid second counter the position of said first counter in order tooperate or not one or more of said inhibition means during said distincttime intervals.

11. Data processing system as claimed in claim 10, wherein saidplurality of gating means are arranged so as to constitute a lock-outcircuit, means responsive to a request registered in one of saidplurality of request registering means for inhibiting all gating meansassociated with higher numbered request registering means, and meanswhereby the request is registered in the associated other requestregistering means, if the associated gating means is itself notinhibited by a request registered in a lower numbered requestregistering means or by one of said inhibition means.

12. Data processing system as claimed in claim 11, characterized in thatsaid request registering means are constituted by first (A; to A andsecond (B to B bistate devices, that each first bistate device has itsl-input coupled to an associated first logical circuit MU to MU whereaseach second bistate device has its l-input coupled to an associatedsecond logical circuit (AC to AC so that a first or second bistatedevice is brought in its l-condition when the associated first or secondcircuit originates a request, that said lock-out circuit is constitutedby a plurality of first (X; to V and second (Y, to Y coincidence gateswhich are each connected to the l-output of a corresponding first (A toA and second (B to B bistate device respectively other inputs of eachfirst said second coincidence gate being connected to the O-inputs ofall the preceding first and second bistate devices and that each of saidother registering means is constituted by a third bistate device (C to CD to D having its l-input coupled to the output of a corresponding firstor second coincidence gate.

13. Data processing system as claimed in claim 12, characterized in thatit includes a single inhibition circuit which is constituted by a fourthbistate device (F) the O-output of which is connected to an input ofsaid second coincidence gates (Y to Y,,) and the l-input of which isconnected to the output of said timing arrangement.

14. Data processing system as claimed in claim 13, characterized in thatsaid first counter has associated to it a number of s third concidencegates (M V V the output of each of which is activated as long as saidfirst counter is in a position between two predetermined positions, thatsaid second counter has associated to it a number of rs fourthcoincidence gates (V V the output of each of which is activated whensaid second counter is in one of r predetermined positions indicating rpredetermined first time positions (T T that the outputs of said s thirdcoincidence gates are each connected to an input of a fifth coincidencegate, (V V V another input of which is connected to one of the outputsof said r fourth coincidence gates and that the output of each of saidfifth coincidence gates is connected to the l-input of said fourthbistate device (F) via a first mixer (W 15. Data processing system asclaimed in claim 14, characterized in that said second counter hasassociated to it a number of s sixth coincidence gates (V V V the outputof each of which is activated as long as said second counter is in oneof s predetermined positions indicating s predetermined other timepositions (T T T and that the outputs of said s sixth coincidence gatesare connected to the O-input of said fourth bistate device via a secondmixer (W,,

16. Data processing system as claimed in claim 15, characterized in thatan input of each of said first and second coincidence gates is connectedto the O-output of a fifth bistate device (E) the l-input of which iscon- 14 nected to the output of a third mixer (W the inputs of which areconnected to the l-outputs of all said third bistate devices.

17. Data processing system as claimed in claim 16, characterized in thatit includes means for activating a terminal (T) each time said commoncontrol circuit has finished its intervention, that said terminal iscoupled to the O-input of each of said first and second bistate devicesvia a seventh coincidence gate (Z, to Z,,, U, to U,,), another input ofwhich is connected to the l-output of the corresponding third bistatedevice, and that said terminal is further coupled to the O-inputs ofsaid third bistate devices and of said fifth bistate device via a delaycircuit (D).

18. Data processing system as claimed in claim 16, characterized in thatthe sequence of said q routine operations is controlled by a pulsegenerator (PG) which is coupled to said first logical circuits via aneighth coincidence gate (K the inputs of which are connected to theO-output of said fifth bistate device (E) and to the O-output of a sixthbistate device (P) respectively, and that the land O-inputs of saidsixth bistate device are connected to the output of the final stages ofsaid first (C and of said second counter (TC) respectively.

19. Data processing system as claimed in claim 3 characterized in thateach of said logical circuits or first logical means has one or morefirst outputs each of which is activated upon a request being originatedby the associated logical circuit or first logical means and each ofwhich is coupled to one of said request registering means, and that anactivated first output gives an indication concerning as well theidentity of the logical circuit or first logical means originating therequest as concerning the reason for which this request is originated.

20. Data processing system as claimed in claim 3, characterized in thateach of said logical circuits or first logical means has one secondoutput (SR) which is activated upon a request being originated by theassociated logical circuit or first logical means and which thenindicates the identity of this logical circuit or first logical meanssaid second output being coupled to one of said request registeringmeans and that each of said logical circuits or first logical means hasone or more third outputs (SC) which are activated simultaneously withsaid second output upon a request being originated by the associatedlogical circuit or first logical means and for a distinct reason forwhich this request is originated.

21. Data processing system as claimed in claim 19 characterized in thatwhen a request is granted the identity of the requesting logical circuitor first logical means as well as the reason for which this request hasbeen granted are transferred to a processing circuit (LC) wherein thisinformation is processed so as to form input information for aprogramming unit (CPU) which delivers output information to control saidlogical circuits or first logical means.

22. Automatic telecommunication switching system including a dataprocessing system as claimed in claim 7, and means for establishing aconnection between a calling and a called subscriber via switching meansand a junctor, means whereby each of said q words stores informationrelating to a connection between a calling and a called subscriber andmore particularly information relating to the identity of a junctor andthe subscriber loop condition indicated by the conditions of saidjunctor used in the establishment of a connection between a calling anda called subscriber, and means whereby each of said q routine operationsis to detect modifications in said subscriber loop condition.

23. Automatic telecommunication system as claimed in claim 22,characterized in that said auxiliary logical circuit comprises a junctorscanner (JSC), a junctor scanning logical circuit (JSLC) and a logicalmeans (SLC), that in interrogating one of said q words the 15 16identity of a junctor and the previous loop condition of and to requestfor an intervention of said common control a particular subscriber areobtained and transferred to circuit. said junctor scanner and saidjunctor scanner logical cir- References Cited cuit respectively, thatsaid junctor scanner checks the UNITED STATES PATENTS present loopcondition of said particular subscriber and 5 transfers it to saidjunctor scanning logical circuit wherein 23361288 3/1952 179-18 it iscompared with the previous loop condition already 4/196 Schnmpf 34O172-5transferred thereto, and that upon a modification being detected anoutput signal is transmitted to said logical ROBERT BAILEY P'lmaryExammer means in order to indicate this modified loop condition 10 R. B.ZACHE, Assistant Examiner.

